March 2011A list of recently published documents, including descriptions and ordering numbers.
On-line versions of these publications are available on the Lattice website at www.latticesemi.com. Some documents are also available in print. To order print versions, call your local Lattice representative or the Lattice Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8693. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
| Title | Description | Web | Order # | |
|---|---|---|---|---|
| Data Sheets & Handbooks | ||||
| MachXO2 Family Data Sheet | Full specifications for the MachXO2 PLD family. Updated for ultra-high I/O (“U”) devices. |  |
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| MachXO2 Family Handbook | MachXO2 Family Data Sheet and technical notes on using the key features of this device family. Updated for ultra-high I/O (“U”) devices. | |
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| Brochures | ||||
| Product Selector Guide | Overview of entire Lattice product line in tabular format. Updated for MachXO2 ultra-high I/O (“U”) devices. | |
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| MachXO2 System Product Brief | Introduction to the Do-it-All PLD family optimized for system applications. Updated for ultra-high I/O (“U”) devices. | |
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| MachXO2 Consumer Product Brief | Introduction to the Do-it-All PLD family optimized for consumer applications. Updated for ultra-high I/O (“U”) devices. | |
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| Technical Notes | ||||
| MachXO2 sysCLOCK PLL Design and Usage Guide | Describes the clock resources available in the MachXO2 devices, including primary clocks, edge clocks, clock dividers, sysCLOCK PLLs, DCC elements, the secondary high fan-out nets, and the internal oscillator. Updated for ultra-high I/O (“U”) devices. | |
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| MachXO2 Density Migration | Describes the density migration capabilities and considerations for MachXO2 devices. Enables system designers to migrate their design to a higher or lower density device without changing the PCB layout. Updated for ultra-high I/O (“U”) devices. | |
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| Memory Usage Guide for MachXO2 Devices | Discusses memory usage for the Lattice MachXO2 PLD family. A guide for integrating the EBR and PFU based memories for these devices in ispLEVER utilizing IPexpress, PMI inference, memory modules and memory primitives. Updated for ultra-high I/O (“U”) devices. | |
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| MachXO2 sysIO Usage Guide | Provides a description of the supported I/O standards and the banking scheme for the MachXO2 PLD family. The sysIO architecture and software usage are also discussed. Updated for ultra-high I/O (“U”) devices. | |
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| Implementing High-Speed Interfaces with MachXO2 Devices | Focuses on the implementation of high-speed generic DDR interfaces, and memory DDR/DDR2 and LPDDR interfaces in MachXO2 devices. Lean to make use of the built-in capabilities of the MachXO2 devices to achieve the best performance for high-speed interfaces. Updated for ultra-high I/O (“U”) devices. | |
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| Using User Flash Memory and Hardened Control Functions in MachXO2 Devices | Learn to use the hardened control functions and on-chip user Flash memory built into the MachXO2 devices. Updated for ultra-high I/O (“U”) devices. | |
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| MachXO2 SED Usage Guide | Describes the hardware-based soft error detect (SED) of the MachXO2 PLDs. Updated for ultra-high I/O (“U”) devices. | |
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